module alu_top(in1,in2,alu_con,zero,result);
  
  input [7:0] in1,in2;
  
  input [2:0] alu_con;
  
  output zero;
  
  output reg [7:0] result;
  
  wire [7:0] _in2,sum,slt;
  
  assign _in2= alu_con[2] ? ~in2:in2;
  
  assign sum = in1 + _in2 + alu_con[2];
  
  assign slt = sum[7];
  
  always @(*)
  begin
    case(alu_con[1:0])
      2'b00 : result <= in1 & _in2;
      2'b01 : result <= in1 | _in2;
      2'b10 : result <= sum;
      2'b11 : result <= slt;
    endcase
  end
  
  assign zero = (result == 0);  
  
endmodule
